Trench capacitor for high density dynamic RAM

ABSTRACT

A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

This invention relates to manufacture of semiconductor devices, and moreparticularly to a dynamic read/write memory cell of the MOS VLSI type.

Semiconductor dynamic RAM devices of the type shown in U.S. Pat. No.4,081,701 issued to White, McAdams and Redwine (a 16K RAM), or U.S. Pat.No. 4,293,993 issued to McAlexander, White and Rao (a 64K RAM), havebeen manufactured by processes of the type described in U.S. Pats. Nos.4,055,444 or 4,388,121, both issued to G. R. M. Rao; all of thesepatents are assigned to Texas Instruments. In order to reduce the sizeof a dynamic RAM cell to the level needed to produce very high densityRAMs, such as the 1-Megabit DRAM, various methods of reducing thecapacitor size have been proposed. The magnitude of the capacitor mustbe maintained at no less than a certain value so that sufficient chargeis stored. One method of reducing capacitor area yet maintainingadequate charge storage is to reduce the oxide thickness as explained inU.S. Pat. No. 4,240,092 issued to Kuo, assigned to Texas Instruments;this approach reaches a limit in the area of about 100 to 200 Å oxidethickness because of yield and reliability problems. Another way ofincreasing the capacitance per unit area is to etch a groove, or trench,in the capacitance region, thus increasing the area; an example of thismethod is shown in U.S. Pat. No. 4,225,945, also assigned to TexasInstruments.

It is the principle object of this invention to provide an improvedprocess for making high density dynamic RAM cells, particularly with anincreased capacitance area due to a trench etched into the storagecapacitor region. Another object is to provide an improved method ofmaking trench capacitor type dynamic RAM cells in which the step ofetching the trench avoids the effect of undercut. A further object is toprovide a simple and reliable process for forming trench capacitors.

SUMMARY OF THE INVENTION

In accordance with one embodiment of the invention, a dynamicone-transistor read/write memory cell employs a trench capacitor toincrease the magnitude of the stored charge. The trench is etched intothe silicon surface at a diffused N+ capacitor region similar to the N+bit line, then thick oxide is grown over the bit line and over thecapacitor region, but not in the trench; a partial etch followed byregrowth of oxide is used prior to the final etch for most of the depthof the trench, to thereby reduce the effect of undercut. The upper plateof the capacitor is a polysilicon layer extending into the trench andalso forming field plate isolation over the face of the silicon bar. Arefractory metal word line forms the gate of the access transistor at ahole in the polysilicon field plate.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asother features and advantages thereof, will be best understood byreference to the detailed description which follows, read in conjunctionwith the accompanying drawings, wherein:

FIG. 1 is a plan view, greatly enlarged, of a small part of a memorycell array in a semiconductor dynamic read/write memory, including amemory cell according to the invention;

FIG. 2 is an elevation view, in section, of the cell of FIG. 1, takenalong the line 2--2 in FIG. 1;

FIG. 3 is an elevation view, in section, of the cell of FIG. 1, takenalong the line 3--3 in FIG. 1;

FIG. 4 is an elevation view, in section, of the cell of FIG. 1, takenalong the line 4--4 in FIG. 1;

FIG. 5 is an electrical schematic diagram of the memory cell of FIGS.1-4; and

FIGS. 6-9 are elevation views in section of the cell of FIGS. 1,corresponding to FIG. 2, at successive stages in the manufacturethereof.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT

Referring to FIGS. 1-5, a one-transistor dynamic memory cell is shownwhich is constructed according to the invention. This cell has anN-channel access transistor 10 and a storage capacitor 11 formed in asilicon substrate 12. The transistor 10 has a metal gate 13 which ispart of an elongated strip 14 forming a row (or word) line for thememory array. The drawin 15 of the transistor is part of an elongatedbit line 16, perpendicular to the word line 14. The portion of thesubstrate shown is a very small part of a silicon bar of perhaps 150×400mils containing 2²⁰ or 1,048,576 of these cells in an array of rows andcolumns, generally as shown in copending application Ser. No. 626,791,filed July 2, 1984, now U.S. Pat. No. 4,630,240 by Poteet & Chang,assigned to Texas Instruments.

The bit line 16 is buried beneath a thick thermal oxide layer 17, so themetal word line can pass directly over the bit line. Isolation laterallyalong the face is provided by a field plate 18, composed of polysiliconin this example, and electrically connected to the substrate voltageVss. A hole 19 in the field plate 18 defines the area of the gate 13 ofthe transistor 10.

According to the invention, the capacitor 11 includes a trench 20, whichis a hole etched into the silicon by an anistropic etch technique suchas RIE. The trench 20 is about one micron wide and three microns deep. Athin silicon oxide layer 21 provides the capacitor dielectric, and thinsilicon oxide 22 the transistor gate insulator. A thicker oxide coating23 and a silicon nitride layer 24 provide the insulator beneath thefield plate 18. The grounded field plate 18 also provides a flat surfacefor the metal line 14, as well as insulating the polysilicon 16 from themetal word line.

The trench 20 and the capacitor 11 are formed in a square area of fieldoxide 28 having a N+ region 29 beneath it, similar to the oxide 17 andbit line 16. This N+ region 29 functions as the source of the accesstransistor 10, and is spaced from the drain 15 by the channel length ofthis transistor.

A method of making the cell of FIGS. 1-5 will be described with respectto FIGS. 6-9. A silicon slice has a layer of thermal silicon oxide 23 ofabout 1000 Å grown on the face, then a layer 24 of silicon nitridedeposited over the oxide. The oxide-nitride sandwich is patterned byphotolithographic steps, leaving an exposed area 30 for the bit line 16and an area 31 where the capacitor will be formed. An ion implant isperformed to creat the N+ regions 32 and 33 which will later form the N+bit line 16 and N+ region 29.

Referring to FIG. 7 an etch mask 34 is deposited for the purpose ofdefining the trench. This etch mask is silicon oxide of a thickness ofabout 8000 Å, formed by low pressure chemical vapor deposition.Photoresist could also be used if the etch selectivity of silicon tophotoresist is high enough. A hole 35 is formed in the layer 34 byphotolithography to define the trench 20. Using an anistropic etch, suchas RIE (reactive ion etch) the trench 20 is created in the capacitorregion to a depth of about three microns. Actually, the bottom of thetrench may be narrower than the top, rather than being squared off, sothe trench may be more cone-shaped than perfectly rectangular, dependingupon the etch process used.

According to the invention, this trench etch is a two-step process. Asseen in the enlarged view of FIG. 7a, the first etch is shallow, andremoves some of the silicon in the hole 35 but also undercuts the mask34 by etching into the region 33 by a small amount at area 36 encirclingthe hole. A thermal oxidation is then performed in steam to grow oxide36a in the area 36, seen in FIG. 7b. Oxide 37 also grows in the trench,but much thinner because of the doping level of the silicon. A dip-outetch removes this oxide in the shallow trench, and so the etch canproceed to the full depth of the trench, using the oxide 36a in the area36 as an etch stop to prevent further undercutting. The extent to whichthis area 36 propogates through to the final structure as a ring 36' ofFIGS. 1, 2 and 4 is very slight.

The trench mask 34 is stripped off, using a conventional oxide etch suchas HF since the etch will stop on the nitride 24. Turning to FIG. 8, theoxide 17 and 28 is now grown over the N+ regions 32 and 33. The oxidegrows many times faster on the N+ silicon than on the very lightly dopedsilicon in the trench 20, so the thickness of the oxide 17 and 28 isabout 4000< while only about 200 Å grows in the trench. This thin oxideis grown in the trench and stripped, then regrown as the oxide 21. Aseen in FIG. 9, a layer of polysilicon is deposited by an isotropicprocess so it coats the sidewalls of the trench and the face of theslice to about the same thickness, to about 2500 Å. Next, an oxide layer26 is deposited over the entire face of the slice to planarize the faceand fill up the trench 20; the oxide 26 will also isolate the word linefrom the face. This polysilicon/oxide stack is patterned usingphotoresist to leave the field plate 18 and capacitor plate 25; i.e.,the hole 19 is cut for the transistor 10.

Referring back to FIGS. 1-4, the oxide in the gate area is stripped andregrown as the oxide 22, and at this point thermal oxide is grown overthe exposed edge of the polysilicon around the periphery of the hole 19.Then the word line is formed by depositing a layer of molybdenum overthe entire face of the slice and patterning it by photolithography toleave the gate 13 and word line 14. A protective coating is added ontop, (not shown) and patterned to expose bonding pads, then the slice istested, scribed and broken into individual bars, and the bars mounted insemiconductor packages.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications to the illustrative embodiments,as well as other embodiments of the invention, will be apparent topersons skilled in the art upon reference to this description. It istherefore contemplated that te appended claims will cover any suchmodifications or embodiments as fall within the true scope of theinvention.

What is claimed:
 1. A dynamic memory cell formed in a face of asemiconductor body, said cell comprising:an access transistor having asource-to-drain path at a channel area of said face, and a metal gateover said channel area separated therefrom by a thin gate oxide; a bitline including an elongated N+ region of said face, the drain of saidtransistor being an edge of said N+ region; a metal word line extendingalong said face perpendicular to said bit line, said metal gate being apart of said word line; said N+ region of said bit line being insulatedfrom said word line by thick thermal field oxide overlying said bitline; a capacitor area at said face including a trench etched into saidface and N+ region surrounding said trench, with a thick thermal fieldoxide overlying said N+ region; a region of thermal field oxideencircling said trench inset into said N+ region surrounding saidtrench, a field plate including a conductive layer covering said faceoverlying said capacitor area, said bit line and all areas except saidchannel area of said transistor, and extending down into said trench toprovide the upper plate of the capacitor, insulated from the silicon insaid trench by a thin oxide.
 2. A memory cell according to claim 1wherein said field plate is insulated from said face in areas exceptsaid capacitor area and said bit line by a layer of oxide and a layer ofsilicon nitride.
 3. A memory cell according to claim 1 wherein saidcapacitor area is spaced laterally along said face from said drainregion by said channel area, and said N+ region in said capacitor areaforms the source of said transistor.
 4. A memory cell according to claim1 wherein said field oxide over said bit line is about the samethickness as the field oxide in said capacitor area.
 5. A memory cellaccording to claim 1 wherein a coating of insulator over said fieldplate fills said trench to provide a level surface for said metal wordline.
 6. A memory cell according to claim 1 wherein the width of saidtrench is no more than about one micron and the depth of the trench isat least about twice the width.
 7. A memory cell according to claim 1wherein said body is P type silicon, said metal word line is molybdenum,and said conductive layer is polysilicon. .Iadd.
 8. A dynamic memorycell formed in a face of a semiconductor body, said cell comprising:anaccess transistor having a source-to-drain path at a channel area ofsaid face, and a gate over said channel area separated therefrom by athin gate oxide; a bit line including an elongated N+ region of saidface, the drain of said transistor being an edge of said N+ region; aword line extending along said face perpendicular to said bit line, saidgate being a part of said word line; said N+ region of said bit linebeing insulated from said word line by thick thermal field oxideoverlying said bit line; a capacitor area at said face including atrench etched into said face and N+ region surrounding said trench, witha thick thermal field oxide overlying said N+ region; a region ofthermal field oxide encircling said trench inset into said N+ regionsurrounding said trench, a field plate including a conductive layercovering said face overlying said capacitor area, said bit line and allareas except said channel area of said transistor, and extending downinto said trench to provide the capacitor, insulated from the silicon insaid trench by a thin oxide. .Iaddend. .Iadd.9. A memory cell accordingto claim 8 wherein said field plate is insulated from said face in areasexcept said capacitor area and said bit line by a layer of oxide and alayer of silicon nitride. .Iaddend. .Iadd.10. A memory cell according toclaim 8 wherein said capacitor area is spaced laterally along said facefrom said drain region by said channel area, and said N+ region in saidcapacitor area forms the source of said transistor. .Iaddend. .Iadd.11.A memory cell according to claim 8 wherein said field oxide over saidbit line is about the same thickness as the field oxide in saidcapacitor area. .Iaddend. .Iadd.12. A memory cell according to claim 8wherein a coating of insulator over said field plate fills said trenchto provide a level surface for said metal word line. .Iaddend. .Iadd.13.A memory cell according to claim 8 wherein the width of said trench isno more than about one micron and the depth of the trench is at leastabout twice the width. .Iaddend. .Iadd.14. A memory cell according toclaim 8 wherein said body is P type silicon, said word line ismolybdenum, and said conductive layer is polysilicon. .Iaddend.